The subject embodiments of the invention relate to superconducting devices, and more specifically, to quantum information devices and methods of fabricating the same. For previously proposed vertical Josephson junctions, only a thin silicon layer operates efficiently. However, having a thin silicon layer increases coupling across circuit layers on opposite sides of the thin silicon layer surfaces. Therefore, use of a thin or a thick layer of silicon will depend on the application. In some cases, there should be both a vertical Josephson junction and a free configuration of interconnections among them.
In addition, when using Silicon-on-Metal (SOM) wafers, it is not possible to remove a bottom superconductor layer while keeping a top superconductor layer. Instead, either both layers are removed, or only the top layer is removed using a standard etch process. If the bottom layer is removed, then filled with dielectric, and a top superconductor layer is deposited, this can increase the loss tangent, which is not preferred in quantum computing applications. However, configurations where a bottom superconductor layer is missing and a top superconductor layer exists are utilized for various circuitry.
For example, Megrant (WO Patent Application 2017116442 A1) discusses that “[a] first wafer [ ] and [a] second wafer [ ] are joined (e.g., bonded) together (506), as shown in the example of FIG. 1C to form a wafer stack.” See paragraph [0035]. “The second wafer [ ] is prepared in the same manner as the first wafer [ ] and includes a substrate [ ], an insulator layer [ ], a single crystalline dielectric layer [ ], and a superconductor layer [ ].” See id. In Megrant, however, there is no means to access the bottom layer and, therefore, the bottom layer does not comprise circuitry.